1. Field of the Invention
The present invention relates to dynamic logic and register functions, and more particularly to a non-inverting domino register that addresses the problem of registering the outputs of complex logic circuits where speed and size are important factors.
2. Description of the Related Art
Integrated circuits use a remarkable number of registers, particularly those having a synchronous pipeline architecture. Register logic is employed to hold the outputs of devices and circuits for a period of time so that these outputs can be received by other devices and circuits. In a clocked system, such as a pipeline microprocessor, registers are used to latch and hold the outputs of a given pipeline stage for a period of one clock cycle so that input circuits in a subsequent stage can receive the outputs during that period while the given pipeline stage is concurrently generating new outputs.
In the past, it has been common practice to precede and follow complex logical evaluation circuits, such as multiple input multiplexers (muxes), multi-bit encoders, etc., with registers to hold the inputs to and the outputs from the evaluation circuits. Generally, these registers have associated setup and hold time requirements, both of which constrain the evaluation circuits in the preceding stage. In addition, registers have corresponding data-to-output time characteristics, which constrain the evaluation circuits in subsequent stages. The “speed” of a register is typically judged in terms of its data-to-output time, that is, the sum of its setup time and clock-to-output time.
Preceding and following a logical evaluation circuit with traditional register circuits introduces delays into a pipeline system whose cumulative effect results in significantly slower operating speeds. More specifically, one notable source of these delays is the data-to-output time requirements that must be satisfied by logical evaluation circuits in order to ensure stable registered outputs. It is desired to reduce these delays to provide additional time in each stage and to thereby increase overall speed of the pipeline system.
A prior and related disclosure, entitled “Non-inverting Domino Register” with Ser. No. 10/640,369, which is incorporated by reference herein, addressed the problems described above. In the prior disclosure, a non-inverting domino register was described which combined logic evaluation functions with their corresponding registers to achieve a faster clock-to-output time than conventional approaches without compromising the stability of its output. The transitions of the output signal of the non-inverting domino register disclosed therein were shown to be very fast in response to transitions of the clock signal in contrast to the slower transition responses of conventional inverting domino registers. The prior non-inverting domino register, however, was not particularly flexible with respect to the evaluation logic, which had to be provided as N-channel logic. Also, the prior non-inverting domino register could potentially experience leakage effects when embodied in a high leakage or high noise process, such as, for example, 90-nanometer (nm) silicon-on-insulator (SOI).
It is desired to provide an improved domino register that provides all of the benefits of the prior non-inverting domino register, and that is further flexible with regard to the domino stage and that is optimum for use in a high leakage or high noise environment.